1. Field of Invention
The present invention pertains to the field of flash memory circuits. More particularly, this invention relates to a temperature compensated reference circuit for overerase correction circuitry in a flash memory.
2. Art Background
Prior flash memories typically contain an array of flash memory cells arranged as a set of rows and columns. Typically, each column of flash memory cells share a corresponding output sensing circuit. Such an output sensing circuit usually compares the current on a corresponding column of the flash cell array to a reference current to determine whether a selected flash memory cell of the column is in a program state or an erase state.
Typically, a flash memory cell in an erase state exhibits high electrical current characteristics which corresponds to a logical one. A flash memory cell in a program state, on the other hand, exhibits low electrical current characteristics which correspond to a logical zero.
Prior flash memories typically include erase circuitry that erases entire groups of flash memory cells simultaneously. Typically, such an erase operation on a flash memory cell involves the application of a negative voltage to the gate of the memory cell and a positive voltage on the source of the memory cell which removes electrons from the floating gate of the memory cell. Such an erase operation typically lowers the threshold voltage (Vt) for the flash memory cell to a low level that corresponds to a high electrical current state of an erased memory cell.
Nevertheless, the process control variations inherent in semiconductor process technologies usually creates a distribution in the level of threshold voltage Vt for a group of newly erased flash memory cells. In addition, some of the newly erased flash memory cells typically retain a negative level of threshold voltage Vt. Such a memory cell that reaches a threshold voltage Vt of less than zero is typically referred to as an overerased memory cell. Typically, the electrical current that flows in such an overerased flash memory cell is referred to as leakage current (Ileak).
Unfortunately, such a negative threshold voltage for erased memory cells may cause electrical current conduction on a column line that is driven by programmed memory cell during a read operation. As a consequence, the programmed memory cell in a low current state can appear to the output sense circuit as an erased memory cell due to the conduction of the overerased memory cell.
Prior flash memories typically implement a leakage correction mode that reduces the leakage current in overerased memory cells to a tolerable level. During a typical leakage correction mode, a relatively high voltage is applied to the drains of the memory cells while the gates and sources of the memory cells are pulled to the ground level. Such an application of voltage levels creates an inversion region in the overerased flash memory cells and causes electrons to be added to the floating gates of the overerased flash memory cells. Such adding of electrons to the floating gate eventually reduces the amount of leakage current in the overerased flash memory cell below the tolerable level.
In addition, prior flash memories typically includes circuitry that controls the duration of the leakage correction mode. FIG. 1 illustrates one prior reference circuit 20 for controlling the duration of the leakage correction mode in a flash memory. A flash memory cell C1 is shown contained within a flash cell array 10. A bias voltage of approximately 1 v is applied by a bit line bias circuit 100 to the drain of the flash memory cell C1 through a pullup transistor Q20 during leakage verification mode. A drain voltage generator 120 applies a correction level voltage to the drain of the flash memory cell C1 during leakage correction mode. In addition, the gate of the flash memory cell C1 is grounded during the leakage correction mode. The level of leakage current in the flash memory cell C1 is sensed via a signal line 22. The reference circuit 20 includes a comparator circuit 12 that compares the level of leakage current for the flash memory cell C1 to a reference current sensed on a signal line 24.
The reference current on the signal line 24 is generated by a sense ratio circuit comprising a set of transistors Q1 through QN. The reference circuit 20 also includes a reference flash memory cell C2. The gate of the reference flash memory cell C2 is coupled to a high voltage source level VX. The electrical current through the reference flash memory cell C2 is divided among the arrangement of parallel pullup transistors Q1 through QN. Typically, the number N is preselected to balance the reference current flowing through the reference flash memory cell C2 to the tolerable level of leakage current in the overerased flash memory cell C1. The comparator circuit 12 generates a control signal 26 to signal an end to leakage correction when the level of leakage current sensed via the signal line 22 falls below the level of current provided the sense ratio circuit on the signal line 24.
Typically, the sense ratio N of the reference circuit 20 is preselected by first determining the tolerable level of electrical leakage current through the overerased cell C1 at the maximum operating temperature of the flash memory. Typically, the maximum operating temperature of the flash memory represents the worst case level of electrical leakage current through the overerased cell C1. The worst case maximum temperature leakage current for the overerased cell C1 is then converted to the corresponding leakage current for the minimum operating temperature of the flash memory. Typically, the sense ratio is then preselected in order to provide the appropriate level of electrical current on a signal line 24 for a minimum operating temperature of the flash memory.
Unfortunately, such selection of a sense ratio at minimum operating temperature based upon a worst case analysis of leakage current at the maximum operating temperature typically causes overcorrection of overerased flash memory cells at high temperatures. Such a technique yields extremely long correction times and possible functional failures at high temperatures if the leakage correction mode was performed at a low temperature. In addition, such long correction time impose a fundamental limit on the available speed for accessing such a flash memory.